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Norm (ノーム) CastoriceBlushing @norm@shrimp.biribiri.dev
4mo
poor powerpc left forgotten
:apensive@akko.wtf:2
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Haelwenn /элвэн/ triskell @lanodan@queer.hacktivis.me
4mo
@norm So got sparc{,64}; alpha; x86_{32,16}; mips{,64}; loongarch; sh4; xtensa; AArch32; m68k; 6502; AVR; Z80; …
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Wolf480pl @wolf480pl@mstdn.io
4mo
@lanodan
@norm
let's not forget hppa and itanium
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Wolf480pl @wolf480pl@mstdn.io
4mo
@lanodan @norm
(let's do forget about 8051)
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Norm (ノーム) CastoriceBlushing @norm@shrimp.biribiri.dev
4mo
@wolf480pl @lanodan forgot VAX
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Wolf480pl @wolf480pl@mstdn.io
4mo
@norm @lanodan
that's a spiritual predecessor of 68k tho
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Norm (ノーム) CastoriceBlushing @norm@shrimp.biribiri.dev
4mo
@wolf480pl @lanodan thought of it more of an alpha predecessor since both are dec architectures
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Wolf480pl @wolf480pl@mstdn.io
4mo
@norm @lanodan
I thought Alpha was RISC tho...

And VAX is like, the epitome of CISC. It has a fuckton of addressing modes, and you can use every single one of them with every instruction, and everything that can be done through addressing modes is done through addressing modes.

It's beautiful and makes it impossible to pipeline.
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Norm (ノーム) CastoriceBlushing @norm@shrimp.biribiri.dev
4mo
@wolf480pl @lanodan it's amazing how x86 was modernized to what it is today despite being similar in many ways
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[GRLC] kasane tito @novenary@akko.wtf
4mo
@norm @wolf480pl @lanodan well modern implementations pretty much JIT it into something more serviceable which helps massively
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Wolf480pl @wolf480pl@mstdn.io
4mo
@novenary @lanodan @norm
it helps that your encoding of immediate operands isn't

*(pc++)

where the PC has to point to the middle of an instruction, and that's where the immediate is expected to be, and the rest of the operand addresses can be after that
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Sun Microdevil Pte Ltd @koakuma@uwu.social
4mo
@novenary @wolf480pl @lanodan @norm Also helps that x86 is "ugly" in ways that doesn't really impact performance (see e.g the absence of mem-mem instructions) blobcatpeekaboo
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Ammar Nofan Faizi @ammarfaizi2@gnuweeb.org
4mo
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Wolf480pl @wolf480pl@mstdn.io
4mo
@ammarfaizi2 @koakuma @novenary @lanodan @norm
huh, I thought movs always takes es:rdi and ds:rsi, no matter what you write...
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Ammar Nofan Faizi @ammarfaizi2@gnuweeb.org
4mo
@wolf480pl @koakuma @novenary @lanodan @norm

Yes, it's always es:rdi and ds:rsi. There is no other operands for movs.

The ISA manual says:
"The locations of the source and destination operands are always specified by the DS:(E)SI and ES:(E)DI registers."

The table says both operands are mem. It's just an explicit form in Assembly language.
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Sun Microdevil Pte Ltd @koakuma@uwu.social
4mo
@ammarfaizi2 @novenary @wolf480pl @lanodan @norm Oh yeah I forgot about the string instructions

Though I do think it's still pretty tame compared to how VAX would actually let you do it with pretty much any operation, see e.g:
godbolt.org/z/e3dPWPvrK

By "tame" I mean the set of possible mem-mem operations are constrained enough that I think Intel did manage to special case them for fast operation in their newer processors
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Sun Microdevil Pte Ltd @koakuma@uwu.social
4mo
@ammarfaizi2 @novenary @wolf480pl @lanodan @norm re: unconstrained addressing mode/op combination, this used to be the goal of ISA designers, but then they realize that such kinds of design is hard to be made fast; x86, by virtue of being a descendant of the 8080 (which is itself not much of an orthogonal ISA), managed to mostly avoid this issue, that's how I understand it

en.wikipedia.org/wiki/Orthogonal_instruction_set
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Haelwenn /элвэн/ triskell @lanodan@queer.hacktivis.me
4mo
@norm @wolf480pl Plus ancient IBM architectures (s390 without an x in fact), PDP-11, …
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